1. Field of the Invention
The present invention relates to the field of boundary-scan interconnect testing of circuit boards. More specifically, the invention relates to a method for reducing the possibility of testing-induced component damage.
2. Background Art
Testing complex digital circuitry at the circuit board level is frequently performed on an ATE (Automated Test Equipment) system. The HP3070 tester is an example of an ATE system. The HP3070 is available from Hewlett-Packard Company, Palo Alto, Calif. Detailed operational information for the HP3070 is contained in "HP3070 Board Test System User's Documentation Set (1989)" available from Hewlett-Packard under HP part number 44930A.
Testing performed on an ATE system includes functional test and in-circuit test. Functional test conventionally involves providing input signals to the external inputs of a circuit board or printed wiring board under test (hereinafter referred to as a "PWB") and observing output signals from the external outputs of the PWB. This type of testing becomes quite complex for large circuits and can provide only limited diagnostics.
Modern testing increasingly supplements this traditional functional test with in-circuit component test. In-circuit component test is a type of functional test wherein the performance of each digital integrated circuit (IC) is tested as a functional unit. That is, each component (e.g., digital IC) on the PWB is tested as if it were electrically isolated from the surrounding circuit. In order to perform the in-circuit component test, the tester (e.g., ATE) must apply input signals directly to the inputs of a DUT (device under test) and must access the outputs of the DUT to observe the output response.
An ATE system, such as the HP3070, uses a "bed-of-nails" (i.e., probes which directly make contact with device I/O pins from pads on the surface of the PWB) fixture to access the required nodes on a PWB. Unfortunately, the nodal access required by in-circuit test is often hampered by increasing circuit complexity (e.g., miniaturized components, multi-chip modules, ASIC's etcetera) and increasing use of such technologies as surface mount and silicon-on-silicon.
The development of boundary-scan has facilitated in-circuit testing by improving nodal access. Boundary-scan is a standardized (e.g., IEEE Standard 1149.1-1990) test technique which involves devices designed with shift registers placed between each device pin and the internal logic of an IC chip. This provides a tester with access to every input and output signal on the boundary-scan chip, and allows the tester to control the I/O pins independent of the core logic and/or to control the core logic independent of the I/O pins.
A detailed discussion on boundary-scan is provided in IEEE Std 1149.1-1990, "IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE Standards Board and "HP Boundary-Scan Tutorial and BSDL Reference Guide," Hewlett-Packard Company, HP part number E1017-90001, which are incorporated herein by reference.
Most relevant to the present invention is the use of boundary-scan for interconnect testing. In production testing of circuit boards, device interconnects (e.g., printed circuit traces) are tested prior to mounting components thereon. Likewise, the components are tested prior to mounting on the PWB. Once the components are mounted, it is desirable to re-test the interconnects. This test is called a boundary-scan interconnect test.
The boundary-scan interconnect test seeks to locate problems which are introduced during installation of the integrated circuit chips (IC's) on the PWB. The primary faults include open-circuits, short-circuits, missing or wrong components, and mis-oriented (e.g., rotated 180.degree.) components. Open-circuits frequently result from broken pins or "cold" solder joints. Short-circuits may be caused by excess solder bridging the gap from one IC pin connection to the next.
An interconnect test involves testing each conductive "net" or "node" on the PWB to ensure that it connects the proper devices (e.g., input and/or output buffers of one or more IC chips). A "net" or "node" is defined as an equipotential surface formed by a physical conductor.
Interconnect faults include single-net faults and multi-net faults. Single-net faults involve only one net and include stuck HIGH, stuck LOW and open-circuit faults. Multi-net faults are caused by short-circuits which connect two or more nets. Single-net faults are simple to detect and locate. Multi-net faults, however, can be difficult to diagnose. For example, two short-circuited nets can "alias" (i.e., behave) identically to a third good net such that it is not possible to determine whether the third good net is also involved in the short-circuit. Similarly, it is possible for two short-circuits, each involving two or more nets, to have the identical behavior such that it is not clear whether there is one large short-circuit or two independent short-circuits. This phenomenon is known as "confounding".
The actual outcome of a multi-net fault will depend on the type of nets involved. The three types of nets include: simple nets, wire nets, and three-state nets. A simple net is driven by a single buffer/driver. A wire net is a net which is driven by more than one buffer/driver. A wire net may be either a wire-AND or a wire-OR net. A wire-AND net is a net having drivers which have a dominant LOW state. That is, if two drivers are shorted together, a LOW signal will dominate such that a logical AND of the signals results. A wire-OR net is a net having drivers which have a dominant HIGH state. That is, if two drivers are shorted together, a HIGH signal will dominate such that a logical OR of the signals results. A three-state net is a net which is driven by more than one three-state buffer/driver.
The result of multi-net faults may be deterministic (predictable) or non-deterministic (non-predictable). Deterministic faults include OR-type shorts (i.e., shorts between wire-OR nets), AND-type shorts (i.e., shorts between wire-AND nets), and strong-driver shorts (i.e., a short between nets wherein a dominant driver controls the state of the nets regardless of other drivers). For a more detailed analysis of fault diagnosis, see N. Jarwala and C. W. Yau, "A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects," Proceedings of International Test Conference 1989, pp. 63-70 (IEEE Order No. CH2742-5/0000/0063), which is incorporated herein by reference.
Diagnosing these different types of interconnect faults can be difficult. A single test vector can detect a fault; however, it provides very little diagnostic information. In order to diagnose a fault condition, a plurality of test vectors are required. The plurality of test vectors must be broadcast, captured, and then analyzed for fault diagnosis. The entire boundary-scan test must be executed in order to provide data which can be analyzed for fault diagnosis. The actual length of the test will be determined by the amount of diagnosis desired.
In performing the interconnect boundary-scan test, it is sought to use a test pattern which will detect a fault (i.e., an interconnect problem) and which will provide diagnostic information useful for locating the fault. A single test vector can detect a fault; however, it provides very little diagnostic information. In order to diagnose a fault condition, a plurality of test vectors are required. This plurality of test vectors is called a "test pattern". The entire test pattern must be broadcast and the resulting data captured before it can be analyzed for fault diagnosis. The entire boundary-scan test must be executed in order to provide data which can be analyzed for fault diagnosis.
It is desirable to provide a test pattern which will provide as complete a diagnosis as can be achieved through boundary-scan interconnect test. In addition, it is desirable to keep the test pattern as short as possible because each test vector must be serially shifted into (and out of) the boundary register one bit each test cycle. Unfortunately, these goals are in direct conflict such that brevity is often sacrificed for diagnostic capability and visa versa.
A test pattern which has brevity as its primary concern is called a brief test pattern. Brief test patterns tend to provide limited diagnostics. A "counting" test pattern is an example of a brief test pattern.
A test pattern which is primarily concerned with diagnostic capabilities is called a high diagnostic test pattern. High diagnostic test patterns tend to be lengthy. A "walking ones" test pattern is an example of a brief test pattern. For an in-depth analysis of test pattern algorithms, see co-pending U.S. Pat. Appl. Ser. No. 07/757,162, titled "AN IMPROVED BOUNDARY-SCAN INTERCONNECT TEST METHOD," filed on Sep. 10, 1991; and U.S. Pat. Appl. Ser. No. 07/794,767, titled "ENHANCED BOUNDARY-SCAN INTERCONNECT TEST DIAGNOSIS THROUGH UTILIZATION OF BOARD TOPOLOGY DATA," filed on Nov. 19, 1991; both of which are incorporated herein by reference.
Regardless of the test pattern used for the boundary-scan test, power must be applied to the circuit in order to perform the interconnect test. While this power is applied, any fault that exists on the PWB may be causing stress to one or more components on the PWB. This stress may damage or destroy the components. For example, a short-circuit between two pins of an IC may produce a low-impedance current path inside the IC chip between the positive logic supply voltage (V.sub.cc) and ground. This type of fault can cause excessive current flow which may destroy bond wires, PWB traces, transistors, etcetera, on the IC chip.
The type of fault which is most likely to cause component damage is a short-circuit. An open-circuit fault rarely poses a damage concern. Damage normally results from excessive current flow through a conductor or other electrical device (e.g., a transistor) which causes excessive heat build-up due to excessive power dissipation (i.e., I.sup.2 R losses). The amount of heat built-up is a function of the length of time that energy is delivered to the device. That is, the longer power is applied to the faulted circuit, the greater is the risk of damage. Thus, in order to reduce the likelihood of damage, it is desirable to test a PWB as quickly as possible so that the total elapsed time from power-up to power-down is small enough to prevent component damage. However, as discussed above, the length of a test is directly related to its diagnostic capabilities, and a certain level of diagnosis must be maintained.
Thus, standard boundary-scan testing methodologies tend to be relatively long such that component damage may occur far prior to completion of the test. Further, the standard tests are not capable of indicating a fault until after diagnosis has been performed. This means that it is not possible to stop the test during execution if a short-circuit condition is present, because the short-circuit cannot be identified and located until after the test is completed.